The present invention relates generally to the data processing field, and more particularly, relates to a method and apparatus for implementing high speed double data rate (DDR) synchronous dynamic random access memory (SDRAM) read interface with reduced across chip line-width variation (ACLV) effects.
DDR SDRAMs use a source synchronous interface for reading and writing data. The source synchronous clock strobe on DDR SDRAMs is named DQS. When data is read from a DDR SDRAM, the DQS clock strobe is driven by the SDRAM. The SDRAM edge aligns the DQS clock strobe with the data. It is the responsibility of the device receiving SDRAM read data to delay the incoming DQS and center the incoming DQS in the middle of the incoming data. Strobe centering relative to data is required to handle skew uncertainty between the DQS and data coming out of the SDRAM, as determined by the SDRAM specification. It is also required to handle skew uncertainty created by card wiring, card loading, and inter-signal interference (ISI). Lastly, DQS centering is required to support the data latch setup and hold times.
When DDR interfaces are operated at high frequencies, tight tolerance is required for the circuitry used to implement the delay of DQS. A common method to account for process variation effects on DQS delay between different manufactured chips is to calibrate DQS delay with reference circuitry during system operation.
U.S. Patent Application Ser. No. 09/617,558 filed Jul. 17, 2000 entitled PROGRAMMABLE COMPENSATED DELAY FOR DDR SDRAM INTERFACE and assigned to the present assignee discloses a programmable compensated delay for a double data rate (DDR) synchronous dynamic random access memory (SDRAM) interface. A programmable compensated delay apparatus includes a reference delay calibration circuit for providing a measured number of delay elements in one cycle. A programmable delay register provides a desired delay value. A conversion logic is coupled to the reference delay calibration circuit and the programmable delay register for receiving both the measured number of delay elements in one cycle and the desired delay value. The conversion logic provides a number of required delay elements. A delay circuit is coupled to the conversion logic for receiving the number of required delay elements and providing the desired delay. A SDRAM control logic provides a refresh start signal to the reference delay calibration circuit for updating the delay circuit during each DRAM refresh. The DQS clock strobe on the DDR SDRAM is applied to the delay circuit and is delayed by the desired delay. The subject matter of the above-identified patent application is incorporated herein by reference, as a part hereof.
In the above-identified arrangement, the reference delay calibration circuit and the delay circuit providing DQS delay use separate physical delay elements. Delay elements are composed of transistors. Although the design of the transistors is identical in the reference delay calibration circuit and the delay circuit providing DQS delay, processing variations occur due to variations on the silicon die in lithography, non-uniform dopant levels, non-uniform etching characteristics, and the like. As used in the following description and claims, the term across chip line-width variation (ACLV) effects include these processing variations lumped together. ACLV can result in two delay elements composed with identical transistor designs to have different delay characteristics. For example, ACLV mistracking between identical transistor designs may be +/xe2x88x9220%.
ACLV mistracking can result in the actual DQS delay elements being either slower or faster than the reference calibration circuitry delay elements. The 20% ACLV uncertainty translates into 20% degradation in the potential DDR SDRAM data transfer rate. This directly impacts on both the latency and bandwidth of DDR SDRAM interfaces.
While the above-identified patent application provides improvements over known arrangements, a need exists for a mechanism for implementing high speed double data rate (DDR) synchronous dynamic random access memory (SDRAM) read interface with reduced across chip line-width variation (ACLV) effects.
A principal object of the present invention is to provide a method and apparatus for implementing high speed double data rate (DDR) synchronous dynamic random access memory (SDRAM) read interface with reduced across chip line-width variation (ACLV) effects. Other important objects of the present invention are to provide such method and apparatus for implementing high speed double data rate (DDR) synchronous dynamic random access memory (SDRAM) read interface with reduced across chip line-width variation (ACLV) effects substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, a method and apparatus are provided for implementing high speed double data rate (DDR) synchronous dynamic random access memory (SDRAM) read interface with reduced across chip line-width variation (ACLV) effects. A delay circuit is utilized for providing a delay output. A calibration clock input is applied to the delay circuit during calibration. A DQS input is applied to the delay circuit following the calibration. A calibration circuitry is utilized for receiving the delay output from the delay circuit and providing a calibration result during calibration. The delay circuit is operatively controlled for providing the delay output responsive to the calibration result.
A programmable compensated delay apparatus includes a delay circuit operatively controlled for providing a delay output. A calibration logic provides a calibration clock input and is coupled to the delay circuit for receiving the delay output and providing a calibration result. A multiplexer coupled to the delay circuit receives a first input and the calibration clock input. Multiplexer selectively applies the calibration clock input to the delay circuit during calibration and applies the first input to the delay circuit following the calibration. A programmable delay register provides a desired delay value. A conversion logic coupled to the calibration logic and the programmable delay register receives both the calibration result and the desired delay value. The conversion logic provides a control output to the delay circuit.